Вопросы радиоэлектроники. 2017; : 27-32
МЕТОДЫ ОПТИМИЗАЦИИ ВРЕМЕНИ ДОСТУПА В ОБЩИЙ КЭШ МНОГОЯДЕРНОГО МИКРОПРОЦЕССОРА
Аннотация
Рассмотрена проблема роста времени доступа при масштабировании распределенного общего кэша. Описаны существующие методы ее решения, такие как привязка страниц к банкам кэша, создание копий строк в ближайшем к ядру банке и миграция строк. Произведена оценка влияния реализации кэша на производительность 16-ядерного процессора.
Список литературы
1. Hardavellas N., Ferdman M., Falsafi B., Ailamaki A. Reactive NUCA: Near-optimal block placement and replication in distributed caches. SIGARCH Comput. Archit. News, 2009, no. 37 (3), pp. 184–195.
2. Beckmann B. M., Marty M. R., Wood D. F. ASR: Adaptive selective replication for CMP caches. Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO ’39, Washington, DC, USA, 2006, pp. 443–454.
3. Кожин А. С., Недбайло Ю. А. Оптимизация общего кэша третьего уровня микропроцессора «Эльбрус‑8С» // Вопросы радиоэлектроники. 2015. № 3 (3). С. 21–30.
4. Asanovic K., Zhang M. Victim migration: Dynamically adapting between private and shared CMP caches. Technical report, Computer Science and Artificial Intelligence Laboratory, 2005.
5. Zhao L., Iyer R., Upton M., Newell D. Towards hybrid last level caches for chip-multiprocessors. SIGARCH Comput. Archit. News, 2008, no. 36 (2), pp. 56–63.
6. Herrero E., Gonzalez J., Canal R. Elastic cooperative caching: An autonomous dynamically adaptive memory hierarchy for chip multiprocessors. Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA’10, New York, 2010, pp. 419–428.
7. Lee H., Cho S., Childers B. R. CloudCache: Expanding and shrinking private caches. Proceedings of the 2011 IEEE17th International Symposium on High Performance Computer Architecture, HPCA’11, Washington, 2011, pp. 219–230.
8. Qureshi M. K., Patt Y. N. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO’39, Washington, 2006, pp. 423–432.
Issues of radio electronics. 2017; : 27-32
METHODS OF SHARED CACHE ACCESS LATENCY OPTIMIZATION IN CHIP MULTIPROCESSORS
Abstract
The paper is dedicated to shared cache scaling problems in a CMP with the focus on cache access latency. The main existing methods of its mitigation are discussed, including page colouring, victim replication, and victim migration. The effect of cache implementation methods on the performance of a 16-core processor is evaluated.
References
1. Hardavellas N., Ferdman M., Falsafi B., Ailamaki A. Reactive NUCA: Near-optimal block placement and replication in distributed caches. SIGARCH Comput. Archit. News, 2009, no. 37 (3), pp. 184–195.
2. Beckmann B. M., Marty M. R., Wood D. F. ASR: Adaptive selective replication for CMP caches. Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO ’39, Washington, DC, USA, 2006, pp. 443–454.
3. Kozhin A. S., Nedbailo Yu. A. Optimizatsiya obshchego kesha tret'ego urovnya mikroprotsessora «El'brus‑8S» // Voprosy radioelektroniki. 2015. № 3 (3). S. 21–30.
4. Asanovic K., Zhang M. Victim migration: Dynamically adapting between private and shared CMP caches. Technical report, Computer Science and Artificial Intelligence Laboratory, 2005.
5. Zhao L., Iyer R., Upton M., Newell D. Towards hybrid last level caches for chip-multiprocessors. SIGARCH Comput. Archit. News, 2008, no. 36 (2), pp. 56–63.
6. Herrero E., Gonzalez J., Canal R. Elastic cooperative caching: An autonomous dynamically adaptive memory hierarchy for chip multiprocessors. Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA’10, New York, 2010, pp. 419–428.
7. Lee H., Cho S., Childers B. R. CloudCache: Expanding and shrinking private caches. Proceedings of the 2011 IEEE17th International Symposium on High Performance Computer Architecture, HPCA’11, Washington, 2011, pp. 219–230.
8. Qureshi M. K., Patt Y. N. Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches. Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO’39, Washington, 2006, pp. 423–432.
