Вопросы радиоэлектроники. 2017; : 22-26
ТРАНСЛЯЦИЯ ВИРТУАЛЬНЫХ АДРЕСОВ DMA-ОБРАЩЕНИЙ В МП ≪ЭЛЬБРУС‑8С2≫
Аннотация
Постоянное увеличение объема оперативной памяти и ужесточение требований к безопасности современных вычислительных средств обусловило поддержку виртуальной адресации DMA-обращений в операционных системах, периферийных интерфейсах и, наконец, в микропроцессорах (МП). В статье рассматривается первая реализация устройства трансляции виртуальных адресов DMA-обращений в МП с архитектурой «Эльбрус» и описываются усовершенствования, введенные для увеличения быстродействия его следующей версии, которая внедрена в МП «Эльбрус‑8С2».
Список литературы
1. AMD I/O Virtualization Technology (IOMMU) Specification Revision 2.0 [Электронный ресурс]. 2011. URL: http://developer. amd.com/wordpress/media/2012/10/48882.pdf
2. Intel Virtualization Technology for Directed I/O (VT-d) Architecture Specification [Электронный ресурс]. October 2014. URL: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
3. Ben-Yehuda M. et al. Utilizing IOMMUs for virtualization in Linux and Xen. Proceedings of the Linux Symposium, 2006. Ottawa, Ontario, Canada.
4. Ben-Yehuda M., Xenidis J., Ostrowski M. Price of Safety: Evaluating IOMMU Performance. Proceedings of the Linux Symposium 2007. Ottawa, Ontario, Canada.
5. ARM SMMU [Электронный ресурс]. URL: https://www.arm.com/products/system-ip/controllers/system-mmu.php
6. Jouppi N. P. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. SIGARCH Comput. Archit. News 18, 3a (1990), pp. 364–373.
7. Amit N., Ben-Yehuda M., Yassour B. A. IOMMU: Strategies for Mitigating the IOTLB Bottleneck. WIOSCA 2010 – Sixth Annual Workshop on the Interaction between Operating Systems and Computer Architecture, Saint Malo, France, Jun 2010.
8. Hennessy J., Patterson D. Computer Architecture: A Quantitative Approach. 5th ed. Morgan Kaufmann, 2011.
Issues of radio electronics. 2017; : 22-26
DMA VIRTUAL ADDRESS TRANSLATION IN «ELBRUS‑8C2» PROCESSOR
Abstract
Continuous increase of main memory size and security requirements growth of modern computers lead to DMA virtual address resolution support in operating systems, I/O interfaces, and processors. In this paper we consider the first implementation of DMA virtual address translation unit in «Elbrus» architecture processor. Then we describe performance improvements of its next version, which has been implemented in «Elbrus‑8C2» processor.
References
1. AMD I/O Virtualization Technology (IOMMU) Specification Revision 2.0 [Elektronnyi resurs]. 2011. URL: http://developer. amd.com/wordpress/media/2012/10/48882.pdf
2. Intel Virtualization Technology for Directed I/O (VT-d) Architecture Specification [Elektronnyi resurs]. October 2014. URL: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
3. Ben-Yehuda M. et al. Utilizing IOMMUs for virtualization in Linux and Xen. Proceedings of the Linux Symposium, 2006. Ottawa, Ontario, Canada.
4. Ben-Yehuda M., Xenidis J., Ostrowski M. Price of Safety: Evaluating IOMMU Performance. Proceedings of the Linux Symposium 2007. Ottawa, Ontario, Canada.
5. ARM SMMU [Elektronnyi resurs]. URL: https://www.arm.com/products/system-ip/controllers/system-mmu.php
6. Jouppi N. P. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. SIGARCH Comput. Archit. News 18, 3a (1990), pp. 364–373.
7. Amit N., Ben-Yehuda M., Yassour B. A. IOMMU: Strategies for Mitigating the IOTLB Bottleneck. WIOSCA 2010 – Sixth Annual Workshop on the Interaction between Operating Systems and Computer Architecture, Saint Malo, France, Jun 2010.
8. Hennessy J., Patterson D. Computer Architecture: A Quantitative Approach. 5th ed. Morgan Kaufmann, 2011.
