Радиопромышленность. 2019; 29: 55-67
Подход к проектированию динамически реконфигугигуемых блоков арбитража для встраиваемых систем
https://doi.org/10.21778/2413-9599-2019-29-3-55-67Аннотация
В настоящее время активно развивается направление разработки динамически реконфигурируемых компонентов для встраиваемых систем на базе FPGA. Однако проекты, разработанные на FPGA, очень сильно уступают по своим характеристикам проектам, реализованным по технологии ASIC с использованием тех же проектных норм. Это существенно ограничивает область применения реконфигурируемых систем на базе FPGA. В статье показана актуальность динамической реконфигурации блоков арбитража, предназначенных для встраиваемых систем. Рассмотрены существующие методы проектирования динамически реконфигурируемых компонентов для технологии ASIC и выполнена оценка их применимости для разработки блоков арбитража – сложных функциональных блоков систем-на-кристалле и сетей-на-кристалле. Предложен подход к проектированию динамически реконфигурируемых блоков арбитража для встраиваемых систем, позволяющий учесть специфические требования к этим блокам.
Список литературы
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Radio industry (Russia). 2019; 29: 55-67
The approach to design of dynamically reconfigurable arbitration units in embedded systems
https://doi.org/10.21778/2413-9599-2019-29-3-55-67Abstract
Today we are seeing an intensive development of dynamically reconfigurable components in the FPGA-based embedded systems. Nevertheless, by their parameters, FPGA-based projects are essentially inferior to those that are on ASIC and the same design rules. This significantly limits applications of the FPGA-based reconfigurable systems. The paper presents relevance of dynamic reconfiguration for arbitration units in embedded systems. There is a review of existing design techniques for ASIC-based dynamically reconfigurable components. They have been also evaluated by applicability for the arbitration unit development (complex function modules for systems-on-chip and networks-on-chip). The authors have proposed the approach to the development of dynamically reconfigurable arbitration units in embedded systems. The approach makes it possible to consider specific requirements to these units.
References
1. Azarian A., Ahmadi M. Reconfigurable Computing Architecture Survey and introduction. Publication 2nd IEEE International Conference on Computer Science and Information Technology, 2009, pp. 269–274. DOI: 10.1109/ICCSIT.2009.5234721.
2. Stensgaard M. B. ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology. Publication Second ACM/IEEE International Symposium on Networks-on-Chip, 2008, pp. 55-64. DOI: 10.1109/NOCS.2008.4492725.
3. Cota E., De Morais Amory A., Lubaszewski M. S. Reliability, Availability and Serviceability of Networks-on-Chip. Springer, 2012, 209 p. DOI: 10.1007/978-1-4614-0791-1.
4. Jafri S., Liang Guang L., Hemani A., Paul K., Plosila J., Tenhunen H. Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes. Microprocessors and Microsystems, 2013, vol. 37, iss. 8, pp. 811–822.
5. Yoonjin K. Reconfigurable Multi-Array Architecture for Low-Power and High-Speed Embedded Systems. Journal of semiconductor technology and science, 2011, vol. 11, no. 3, pp. 207–220.
6. O’Connor I., Hassoune I., Navarro D. Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs. VLSI-SoC: Design Methodologies for SoC and SiP. Springer, Berlin, Heidelberg, 2010, vol. 313, pp. 97–113.
7. Hassoune I., O’Connor I. Double-Gate MOSFET Based Reconfigurable Cells. Electronics Letters, 2007, no. 43 (23), pp. 1273–1274.
8. Speedcore eFPGA Datasheet (DS003). Achronix Semiconductor Corporation [Elektronnyi resurs]. URL: https://www.achronix.com/doc/speedcore-efpga-datasheet-ds003/ (data obrashcheniya: 08.07.2019).
9. Electronic Lab. open source hardware projects [Elektronnyi resurs]. URL: http://www.electronics-lab.com/taking-advantage-embedded-fpga-efpga (data obrashcheniya: 08.07.2019).
10. ARC Processor Core. Fujitsu Microelectronics America, INC., 2016 [Elektronnyi resurs]. URL: https://www.fujitsu.com/cn/en/Images/arc_rev3-en.pdf (data obrashcheniya: 11.07.2019).
11. Sklyarov V., Skliarova I. Synthesis of parallel hierarchical finite state machines. In Proceedings of the 2013 21st Iranian Conference on Electrical Engineering, ICEE 2013, pp. 1–8. DOI: 10.1109/IranianCEE.2013.6599683.
12. Glaser J., Damm M., Haase J., Grimm C. TR-FSM: Transition-based Reconfigurable finite state machine. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2011, vol. 4, no. 3 pp. 1–15. DOI: 10.1145/2000832.2000835.
13. Design of Reconfigurable Logic Controllers. In: Karatkevich A., Bukowiec A., Doligalski M., Tkacz J., ed. Berlin, Springer International Publishing AG, 2016, 185 p.
14. Garcia-Vargas I., Senhadji-Navarro R. Finite state machines with input multiplexing: A performance Study. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015, vol. 34, no. 5, pp. 867–871.
15. Gupta S., Pareek V., Jain S. C., Jain D. Realization of sequential reversible circuit from finite state machine. In Proceedings of the International Computer Science and Engineering Conference, ICSEC, 2014, Khon Kaen, Thailand, pp. 458–463. DOI: 10.1109/ICSEC.2014.7024295.
16. Salauyou V. Synthesis of high-speed finite state machines in FPGAs by state splitting. In Computer Information Systems and IndustrialManagement: 15th IFIPTC8 International Conference, CISIM, 2016, pp. 741–751. DOI: 10.1007/978-3-319-45378-1_64.
17. Xydis S., Economakos G., Soudris D., Pekmestzi K. High Performance and area efficient flexible DSP data path synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011, vol. 19, no. 3, pp. 429–442.
18. Leibson S., Kim J. A New Era in chip Design. IEEE, 2005, pp. 51–59.
19. Xtensa LX7 Processor [Elektronnyi resurs]. URL: https://ip.cadence.com/uploads/1099/TIP_PB_Xtensa_lx7_FINAL-pdf (data obrashcheniya: 11.07.2019).
20. ARC Processor Core. Fujitsu Microelectronics America, INC., 2016 [Elektronnyi resurs]. URL: https://www.fujitsu.com/cn/en/Images/arc_rev3-en.pdf (data obrashcheniya: 11.07.2019).
21. Kapasi U. J., Rixner S., Dally W. J., Khailany B., Jung Ho Ahn, Mattson P., Owens J. D. Programmable stream processors. Computer, 2003, vol. 36, iss. 8, pp. 54–62. DOI: 10.1109/MC.2003.1220582.
22. Pasricha S., Dutt N. On-Chip Communication Architectures. System-on-Chip Interconnect. Elsevier, 2008, 544 p.
23. Wiefereink A., Meyr H., Leupers R. Retargetable Processor System Integration into Multi-Processor System-on-Chip Network, Springer Netherlands, 2008. 162 p.
24. Rios-Navarro A., Tapiador-Morales R., Jimenez-Fernandez A., Dominguez-Morales M., Amaya C., Linares-Barranco A. Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator. IEEE 18th International Conference on Nanotechnology (IEEE-NANO), 2018. DOI: 10.1109/NANO.2018.8626313.
25. Rohita P. Patil, Pratima V. Sangamkar. A Review of System-On-Chip Bus Protocols. International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, vol. 4, iss. 1, Jan 2015, pp. 271–281.
26. Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Suvinay Subramanian, Anantha P. Chandrakasan, Li-Shiuan Peh. SMART: A Single-Cycle Reconfigurable NoC for SoC Applications. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 7 p. DOI: 10.7873/DATE.2013.080.
27. Vestias M. P., Neto H. C. A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation. 2006 International Conference on Field Programmable Logic and Applications, 2006, pp. 1–4. DOI: 10.1109/FPL.2006.311303.
28. Hui Liu, Linquan Xie, Jiansheng Liu, Lei Ding. Application of Butterfly Clos-Network in Network-on-Chip. ScientificWorld Journal, 2014, vol. 2014, pp. 1–11.
